Integrated circuit capacitors are widely used in integrated circuit devices. For example, in Dynamic Random Access Memory (DRAM) devices, integrated circuit capacitors may be used to store charge thereon and thereby store data. As the integration density of DRAM devices continues to increase, it is desirable to maintain sufficiently high storage capacitance while decreasing the area of the integrated circuit substrate that is occupied by each capacitor.
When the integration density of the integrated circuit capacitors is increased, it may become more difficult to align the capacitor lower electrode, also referred to as a storage node, to an underlying contact hole. Moreover, in order to allow relatively high capacitance while decreasing the substrate surface area of the capacitor, the height of the storage node may increase as the area decreases. For example, the height of the storage node may increase to one micron or more in a stacked capacitor structure. This may result in a high aspect ratio of the storage node, for example, an aspect ratio exceeding 5. This high aspect ratio may make it difficult to pattern a thick conductive layer to form the storage nodes.
FIGS. 1 and 2 are cross-sectional views of DRAM cell capacitors which are fabricated by conventional methods, respectively taken along the word line direction and along the bit line direction of the DRAM device. As shown in FIGS. 1 and 2, a plurality of field effect transistors 3 are formed in an integrated circuit substrate 2 such as a monocrystalline silicon substrate. The field effect transistors 3 include insulated gate electrodes 7 with an insulating sidewall and capping layer 9 thereon. A plurality of spaced-apart source/drain regions 5 are also included in the integrated circuit substrate 2. Contact pads 4 are connected to respective source/drain regions 5. A first insulating layer such as a first oxide layer 6 is formed on the integrated circuit substrate 2 and a plurality of conductive lines such as bit lines 8 are formed thereon. A second insulating layer such as a second oxide layer 10 is formed on the first oxide layer 6 and on the bit lines 8.
A plurality of contact openings 11 are formed in the second and first oxide layers 10 and 6 to expose the contact pads 4. A conductive layer, preferably comprising polysilicon, is formed on the second oxide layer 10 including in the contact openings 11 at a thickness that determines the height of the storage node. An antireflective layer 13 is formed on the polysilicon layer in order to increase photolithographic resolution. The photoresist layer is formed on the antireflective layer 13 and patterned.
Using the patterned photoresist 14, the antireflective layer 13 and the polysilicon layer are anisotropically etched, for example using plasma etching gas containing sulfur hexafluoride (SF.sub.6) and nitrogen (N.sub.2) to form storage nodes 12. As is well known to those having skill in the art, an overetching process, for example using chlorine and nitrogen gas may be used during the step of etching a very tall polysilicon layer (for example about 10,000 .ANG.ngstroms in thickness) so as to obtain etching uniformity.
Unfortunately, during etching of the storage nodes 12, lateral etching may also occur, especially during the overetching process, which may cause a storage node to break. More specifically, as the etching process continues to expose the upper surface of the second oxide layer 10, the exposed surface of the second oxide layer 10 may be charged by ions of the etching gases, i.e., SF.sub.6.sup.+, Cl.sub.2.sup.+, and N.sub.2.sup.+, due to the large etch selectivity between the polysilicon layer and the underlying oxide layer 10. Therefore, etching ions that flow downstream in the direction of arrows 17 during the overetching process may be repelled by the charged oxide surface, thereby shifting the etching direction laterally towards the bottom sidewalls of the storage nodes 12 as shown by arrows 17. Therefore, the bottom sidewalls of the storage node may become etched due to shifting in etching direction as shown at reference numeral 18. Moreover, if misalignment occurs, the lateral and/or vertical overetching of the storage node may attack the misaligned portion and cause the storage node to break or become unduly thin.